Design for Testability I: from Full Scan to Partial Scan
نویسنده
چکیده
As can be seen in Figure 6.1, there is a stage called test development where it basically consists of three activities; test generation, fault simulation and design for testability implementation. Test generation is a method of generating an input sequence that can distinguish between good chip and defective chip when the input sequence (test sequence) is applied to the chip using a tester. Fault simulation is a step of simulating circuits in the presence of faults. This step is used to evaluate the quality of a set of test sequence by indicating the fault coverage of the test sequence applied to a circuit. Fault simulation is used to generate a minimal set of test sequence as well. Note that test generation and fault simulation are done prior to fabrication. Besides, design for testability (DFT) is also considered before manufacturing process. DFT is a method that augments a circuit so that it is testable.
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